1. Field of the Invention
The present invention relates generally to a data processing apparatus that conforms to the IEEE (Institute for Electrical and Electronics Engineers) 1394 serial interface standards. More particularly, the invention relates to a data processing apparatus suitable for rapid processing of a vast amount of reception and transmission data.
2. Description of the Related Art
In today's multimedia environment, interfaces need to be able to transfer an increased amount of data between a personal computer and peripheral devices and need to have a fast transfer speed. Peripheral devices in the multimedia environment include, for example, a digital video camera and a digital VCR (Video Cassette Recorder), or a color page printer. These peripheral devices tend to handle a vast amount of audio data and/or moving picture data. The IEEE 1394 standard is applied to, for example, a serial interface which couples peripheral devices to a personal computer. The IEEE 1394 protocol permits a vast amount of sequential moving picture data to be transferred in real time. The IEEE 1394 protocol includes an isochronous transfer mode and an asynchronous transfer mode. In the isochronous transfer mode, data is transferred packet (Isoc packet) by packet every predetermined period (125 .mu.s). In the asynchronous transfer mode, a free time in each predetermined period excluding the time in which an Isoc packet should be transferred is used for data transfer. Transferring moving picture data to a computer every given time in the isochronous transfer mode allows the computer to continuously reproduce moving pictures. Accordingly, the IEEE 1394 protocol facilitates reproduction of quality moving pictures.
As shown in FIG. 1, a conventional IEEE 1394 protocol controller (IPC) 80 that is incorporated in a personal computer 100 is connected to a peripheral device 90 by an IEEE 1394 bus cable 92 and is connected to a microprocessor unit (MPU) by an MPU bus cable 94. The IPC 80 includes a protocol control circuit 81, a data storage memory 82 comprised of an FIFO register, an IEEE 1394 interface 83 and an MPU interface 84.
In the isochronous transfer mode, the IEEE 1394 interface 83 receives isochronous (Isoc) packets 86 and 88 from the peripheral device 90 every period of 125 .mu.s or every Isoc cycle as shown in FIG. 2 and supplies those Isoc packets to the protocol control circuit 81. Each Isoc packet 86 or 88 includes transfer data 86b or 88b and a header 86a or 88b affixed to the head of the associated transfer data 86b or 88b. For example, moving picture data, which cannot be transferred in one Isoc cycle due to its large amount, is separated into a plurality of packets, which are transferred over several cycles. At the time of transfer, the headers 86a and 88a are affixed to the respective Isoc packets 86 and 88. The protocol control circuit 81 receives the Isoc packet 86 or 88 and checks if the Isoc packet is to be stored in a memory based on the header 86a or 88a of the received Isoc packet. Data to be transferred on the IEEE 1394 bus cable 92 is serial data. Serial data in an Isoc packet to be stored in the memory is converted by the protocol control circuit 81 to parallel data which is in turn stored in the storage memory 82. The MPU interface 84 reads an Isoc packet from the storage memory 82 and transfers that Isoc packet to the MPU 85 via the MPU bus 94. The MPU 85 performs data processing in accordance with information included in the header of the Isoc packet.
In the asynchronous transfer mode, as shown in FIG. 2, the IEEE 1394 interface 83 receives an asynchronous (Asyn) packet 87 from the peripheral device 90 in a free time in one Isoc cycle excluding the transfer time for the Isoc packet 86. The Asyn packet 87 includes transfer data 87b and a header 87a affixed to the head of the transfer data 87b. The protocol control circuit 81 receives the Asyn packet 87 from the IEEE 1394 interface 83 and checks if this Asyn packet 87 is to be stored in the memory based on the header 87a of the Asyn packet 87. Serial data in the Asyn packet to be stored in the memory is converted to parallel data which is in turn stored in the storage memory 82. The MPU interface 84 reads an Asyn packet from the storage memory 82 and transfers that Asyn packet to the MPU 85 via the MPU bus 94. The MPU 85 performs data processing in accordance with information included in the header of the Asyn packet.
The IPC 80 receives the Isoc packet 86 and the Asyn packet 87 transferred in the first Isoc cycle and the Isoc packet 88 transferred in the next Isoc cycle, and supplies the Isoc packet 86, the Asyn packet 87, data 89 for the controller's control processing and the Isoc packet 88 to the MPU 85 in order. The data 89 for the controller's control processing, which is produced by the IPC 80 or the MPU 85, includes command data for data processing by the MPU 85 and IPC 80. This IPC 80, however, suffers a shortcoming such that the supply of the Isoc packet 88 in the next Isoc cycle is delayed by the supply of the Asyn packet 87 and the data 89 for the controller's control processing which have been transferred in the previous Isoc cycle. In other words, the IPC 80 cannot transfer the next Isoc packet during transfer of an Asyn packet or during the controller's control operation. This problem makes it difficult to accomplish the continuous and real-time reproduction of moving pictures with reality.
The conventional IPC 80 supplies the individual packets 86, 87 and 88, with the headers 86a, 87a and 88a affixed to the respective transfer data 86b, 87b and 88b, to the MPU 85. The MPU 85 analyzes the individual headers 86a, 87a and 88a and handles the moving picture data 86b and 88b, separated into the respective packets 86 and 88, as continuous data. The MPU 85 sequentially removes the headers 86a, 87a and 88a from the Isoc packet 86, the Asyn packet 87 and the Isoc packet 88 after analysis to form continuous data. This formation of continuous data increases a load on the MPU 85 and reduces the data processing speed of the MPU 85. As a result, with the conventional IPC 80, it is difficult to accomplish the continuous and real-time reproduction of moving pictures with reality. Further, the MPU 85 affixes a header to each transfer data to form a packet at the time of data transmission. This header formation processing during data transmission also increases the load on the MPU 85.